Sample Waveforms for pll.vhd

Sample behavioral waveforms for design file pll.vhd

The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design pll.vhd. The design pll.vhd has Cyclone II PLL_TYPE pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 40000 ps. Output port LOCKED will go high when the PLL locks to the input clock.

Fig. 1 : Wave showing NORMAL mode operation.